/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
 *
 * Author: Joseph Chen <chenjh@rock-chips.com>
 */

#ifndef _CRU_RKX120_H

#include "cru_core.h"

// ======================== TXCRU module definition START ======================
// TXCRU_SOFTRST_CON01(Offset:0x404)
#define RKX120_SRST_PRESETN_TX_CRU           0x00000010
#define RKX120_SRST_PRESETN_TX_GRF           0x00000011
#define RKX120_SRST_PRESETN_TX_GPIO0         0x00000012
#define RKX120_SRST_DRESETN_TX_GPIO0         0x00000013
#define RKX120_SRST_PRESETN_TX_GPIO1         0x00000014
#define RKX120_SRST_DRESETN_TX_GPIO1         0x00000015
#define RKX120_SRST_PRESETN_TX_EFUSE         0x00000016
#define RKX120_SRST_RESETN_TX_EFUSE          0x00000017
#define RKX120_SRST_PRESETN_MIPI_GRF_TX0     0x0000001A
#define RKX120_SRST_PRESETN_MIPI_GRF_TX1     0x0000001B
#define RKX120_SRST_PRESETN_TX_I2C2APB       0x0000001E
#define RKX120_SRST_PRESETN_TX_I2C2APB_DEBUG 0x0000001F

// TXCRU_SOFTRST_CON02(Offset:0x408)
#define RKX120_SRST_HRESETN_DVP_TX 0x00000020

// TXCRU_SOFTRST_CON03(Offset:0x40C)
#define RKX120_SRST_PRESETN_CSITX0         0x00000030
#define RKX120_SRST_RESETN_TXBYTEHS_CSITX0 0x00000031
#define RKX120_SRST_RESETN_TXESC_CSITX0    0x00000032
#define RKX120_SRST_PRESETN_CSITX1         0x00000034
#define RKX120_SRST_RESETN_TXBYTEHS_CSITX1 0x00000035
#define RKX120_SRST_RESETN_TXESC_CSITX1    0x00000036
#define RKX120_SRST_PRESETN_DSITX          0x00000038

// TXCRU_SOFTRST_CON04(Offset:0x410)
#define RKX120_SRST_PRESETN_RKLINK_RX        0x00000040
#define RKX120_SRST_RESETN_I2S_SRC_RKLINK_RX 0x00000041
#define RKX120_SRST_RESETN_E0_RKLINK_RX      0x00000045
#define RKX120_SRST_IRESETN_C_CSI0           0x00000046
#define RKX120_SRST_RESETN_E1_RKLINK_RX      0x00000049
#define RKX120_SRST_IRESETN_C_CSI1           0x0000004A

// TXCRU_SOFTRST_CON05(Offset:0x414)
#define RKX120_SRST_DRESETN_C_DVP 0x00000051
#define RKX120_SRST_RESETN_LVDS0  0x0000005B
#define RKX120_SRST_RESETN_LVDS1  0x0000005D

// TXCRU_SOFTRST_CON06(Offset:0x418)
#define RKX120_SRST_RESETN_PMA2PCS2LINK_LINK  0x00000061
#define RKX120_SRST_RESETN_PMA2PCS2LINK_PCS0  0x00000062
#define RKX120_SRST_RESETN_PMA2PCS2LINK_PCS1  0x00000063
#define RKX120_SRST_PRESETN_D_DSI_PATTERN_GEN 0x00000064
#define RKX120_SRST_PRESETN_LVDS0_PATTERN_GEN 0x00000065
#define RKX120_SRST_PRESETN_LVDS1_PATTERN_GEN 0x00000066
#define RKX120_SRST_DRESETN_D_DSI_PATTERN_GEN 0x00000067
#define RKX120_SRST_RESETN_LVDS0_PATTERN_GEN  0x00000068
#define RKX120_SRST_RESETN_LVDS1_PATTERN_GEN  0x00000069

// TXCRU_SOFTRST_CON07(Offset:0x41C)
#define RKX120_SRST_PRESETN_PCS0       0x00000070
#define RKX120_SRST_RESETN_2X_PMA2PCS0 0x00000071
#define RKX120_SRST_RESETN_LINK_PCS0   0x00000073
#define RKX120_SRST_PRESETN_PCS0_ADA   0x00000074
#define RKX120_SRST_RESETN_PCS0_ADA    0x00000075

// TXCRU_SOFTRST_CON08(Offset:0x420)
#define RKX120_SRST_PRESETN_PCS1       0x00000080
#define RKX120_SRST_RESETN_2X_PMA2PCS1 0x00000081
#define RKX120_SRST_RESETN_LINK_PCS1   0x00000083
#define RKX120_SRST_PRESETN_PCS1_ADA   0x00000084
#define RKX120_SRST_RESETN_PCS1_ADA    0x00000085

// TXCRU_SOFTRST_CON09(Offset:0x424)
#define RKX120_SRST_PRESETN_DVPTX      0x00000090
#define RKX120_SRST_PRESETN_MIPITXPHY0 0x00000098
#define RKX120_SRST_RESETN_MIPITXPHY0  0x00000099
#define RKX120_SRST_PRESETN_MIPITXPHY1 0x0000009A
#define RKX120_SRST_RESETN_MIPITXPHY1  0x0000009B

// TXCRU_SOFTRST_CON10(Offset:0x428)
#define RKX120_SRST_PRESETN_PWM_TX 0x000000A0
#define RKX120_SRST_RESETN_PWM_TX  0x000000A1

// TXCRU_SOFTRST_CON11(Offset:0x42C)
#define RKX120_SRST_PRESETN_DFT2APB 0x000000B0

// TXCRU_GATE_CON00(Offset:0x300)
#define RKX120_CLK_TESTOUT_TOP_GATE 0x00000000
#define RKX120_BUSCLK_TX_PRE0_GATE  0x00000001
#define RKX120_BUSCLK_TX_PRE_GATE   0x00000002

// TXCRU_GATE_CON01(Offset:0x304)
#define RKX120_PCLK_TX_CRU_GATE           0x00000010
#define RKX120_PCLK_TX_GRF_GATE           0x00000011
#define RKX120_PCLK_TX_GPIO0_GATE         0x00000012
#define RKX120_DCLK_TX_GPIO0_GATE         0x00000013
#define RKX120_PCLK_TX_GPIO1_GATE         0x00000014
#define RKX120_DCLK_TX_GPIO1_GATE         0x00000015
#define RKX120_PCLK_TX_EFUSE_GATE         0x00000016
#define RKX120_CLK_TX_EFUSE_GATE          0x00000017
#define RKX120_PCLK_MIPI_GRF_TX0_GATE     0x0000001A
#define RKX120_PCLK_MIPI_GRF_TX1_GATE     0x0000001B
#define RKX120_PCLK_TX_I2C2APB_GATE       0x0000001E
#define RKX120_PCLK_TX_I2C2APB_DEBUG_GATE 0x0000001F

// TXCRU_GATE_CON02(Offset:0x308)
#define RKX120_HCLK_DVP_TX_GATE 0x00000020

// TXCRU_GATE_CON03(Offset:0x30C)
#define RKX120_PCLK_CSITX0_GATE                   0x00000030
#define RKX120_CLK_TXBYTEHS_DSITX_CSITX0_DFT_GATE 0x00000031
#define RKX120_CLK_TXESC_CSITX0_GATE              0x00000032
#define RKX120_PCLK_CSITX1_GATE                   0x00000034
#define RKX120_CLK_TXBYTEHS_CSITX1_DFT_GATE       0x00000035
#define RKX120_CLK_TXESC_CSITX1_GATE              0x00000036
#define RKX120_PCLK_DSITX_GATE                    0x00000038
#define RKX120_CLK_RXESC_DSITX_DFT_GATE           0x0000003A

// TXCRU_GATE_CON04(Offset:0x310)
#define RKX120_PCLK_RKLINK_RX_GATE        0x00000040
#define RKX120_CLK_I2S_SRC_RKLINK_RX_GATE 0x00000041
#define RKX120_E0_CLK_RKLINK_RX_PRE_GATE  0x00000044
#define RKX120_E0_CLK_RKLINK_RX_GATE      0x00000045
#define RKX120_ICLK_C_CSI0_GATE           0x00000046
#define RKX120_E1_CLK_RKLINK_RX_PRE_GATE  0x00000048
#define RKX120_E1_CLK_RKLINK_RX_GATE      0x00000049
#define RKX120_ICLK_C_CSI1_GATE           0x0000004A

// TXCRU_GATE_CON05(Offset:0x314)
#define RKX120_DCLK_RGB_GATE      0x00000050
#define RKX120_DCLK_C_DVP_GATE    0x00000051
#define RKX120_DCLK_D_DSI_CM_GATE 0x00000058
#define RKX120_DCLK_D_DSI_GATE    0x00000059
#define RKX120_CLK_LVDS0_CM_GATE  0x0000005A
#define RKX120_CLK_LVDS0_GATE     0x0000005B
#define RKX120_CLK_LVDS1_CM_GATE  0x0000005C
#define RKX120_CLK_LVDS1_GATE     0x0000005D

// TXCRU_GATE_CON06(Offset:0x318)
#define RKX120_CLK_PMA2PCS2LINK_CM_GATE    0x00000060
#define RKX120_CLK_PMA2PCS2LINK_LINK_GATE  0x00000061
#define RKX120_CLK_PMA2PCS2LINK_PCS0_GATE  0x00000062
#define RKX120_CLK_PMA2PCS2LINK_PCS1_GATE  0x00000063
#define RKX120_PCLK_D_DSI_PATTERN_GEN_GATE 0x00000064
#define RKX120_PCLK_LVDS0_PATTERN_GEN_GATE 0x00000065
#define RKX120_PCLK_LVDS1_PATTERN_GEN_GATE 0x00000066
#define RKX120_DCLK_D_DSI_PATTERN_GEN_GATE 0x00000067
#define RKX120_CLK_LVDS0_PATTERN_GEN_GATE  0x00000068
#define RKX120_CLK_LVDS1_PATTERN_GEN_GATE  0x00000069

// TXCRU_GATE_CON07(Offset:0x31C)
#define RKX120_PCLK_PCS0_GATE           0x00000070
#define RKX120_CLK_2X_PMA2PCS0_DFT_GATE 0x00000071
#define RKX120_CLK_LINK_PCS0_DFT_GATE   0x00000072
#define RKX120_CLK_LINK_PCS0_GATE       0x00000073
#define RKX120_PCLK_PCS0_ADA_GATE       0x00000074
#define RKX120_CLK_PCS0_ADA_GATE        0x00000075

// TXCRU_GATE_CON08(Offset:0x320)
#define RKX120_PCLK_PCS1_GATE           0x00000080
#define RKX120_CLK_2X_PMA2PCS1_DFT_GATE 0x00000081
#define RKX120_CLK_LINK_PCS1_DFT_GATE   0x00000082
#define RKX120_CLK_LINK_PCS1_GATE       0x00000083
#define RKX120_PCLK_PCS1_ADA_GATE       0x00000084
#define RKX120_CLK_PCS1_ADA_GATE        0x00000085

// TXCRU_GATE_CON09(Offset:0x324)
#define RKX120_PCLKOUT_DVPTX_GATE   0x00000090
#define RKX120_PCLK_MIPITXPHY0_GATE 0x00000098
#define RKX120_PCLK_MIPITXPHY1_GATE 0x0000009A

// TXCRU_GATE_CON10(Offset:0x328)
#define RKX120_PCLK_PWM_TX_GATE          0x000000A0
#define RKX120_CLK_PWM_TX_GATE           0x000000A1
#define RKX120_CLK_CAPTURE_PWM_TX_GATE   0x000000A2
#define RKX120_CLK_TXESC_MIPITXPHY0_GATE 0x000000A8

// TXCRU_GATE_CON11(Offset:0x32C)
#define RKX120_PCLK_DFT2APB_GATE 0x000000B0

// TXCRU_CLKSEL_CON00(Offset:0x100)
#define RKX120_TEST_CLKOUT_IOUT_DIV                           0x08000000
#define RKX120_TEST_CLKOUT_IOUT_SEL                           0x05080000
#define RKX120_TEST_CLKOUT_IOUT_SEL_XIN_OSC0_FUNC             0U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXPLL_MUX             1U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_CPLL_MUX              2U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_CSITX0       3U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_CSITX0          4U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_CSITX1       5U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_CSITX1          6U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_DSITX        7U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_RXESC_DSITX           8U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LINK_PCS0             9U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LINK_PCS1             10U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_PMARX0_PIXEL      11U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_PMARX1_PIXEL      12U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY0_LVDS   13U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY0_PIXEL  14U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY1_LVDS   15U
#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY1_PIXEL  16U
#define RKX120_TEST_CLKOUT_IOUT_SEL_BUSCLK_TX_PRE             17U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_I2S_SRC_RKLINK_RX     20U
#define RKX120_TEST_CLKOUT_IOUT_SEL_E0_CLK_RKLINK_RX_PRE      21U
#define RKX120_TEST_CLKOUT_IOUT_SEL_PCLKOUT_DVPTX             22U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_DSITX_CSITX0 23U
#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_C_DVP_SRC            24U
#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_D_DSI_SRC            25U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LVDS0_SRC             26U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LVDS1_SRC             27U
#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_RGB_SRC              28U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_2X_PMA2PCS0           29U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_2X_PMA2PCS1           30U
#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_MIPITXPHY0      31U

// TXCRU_CLKSEL_CON01(Offset:0x104)
#define RKX120_BUSCLK_TX_PRE0_DIV               0x06000001
#define RKX120_BUSCLK_TX_PRE0_SEL               0x01070001
#define RKX120_BUSCLK_TX_PRE0_SEL_CLK_TXPLL_MUX 0U
#define RKX120_BUSCLK_TX_PRE0_SEL_CLK_CPLL_MUX  1U
#define RKX120_BUSCLK_TX_PRE_SEL                0x01080001
#define RKX120_BUSCLK_TX_PRE_SEL_XIN_OSC0_FUNC  0U
#define RKX120_BUSCLK_TX_PRE_SEL_BUSCLK_TX_PRE0 1U

// TXCRU_CLKSEL_CON03(Offset:0x10C)
#define RKX120_CLK_TXESC_CSITX0_DIV               0x08000003
#define RKX120_CLK_TXESC_CSITX0_SEL               0x020E0003
#define RKX120_CLK_TXESC_CSITX0_SEL_CLK_TXPLL_MUX 0U
#define RKX120_CLK_TXESC_CSITX0_SEL_CLK_CPLL_MUX  1U
#define RKX120_CLK_TXESC_CSITX0_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON04(Offset:0x110)
#define RKX120_CLK_TXESC_CSITX1_DIV               0x08000004
#define RKX120_CLK_TXESC_CSITX1_SEL               0x020E0004
#define RKX120_CLK_TXESC_CSITX1_SEL_CLK_TXPLL_MUX 0U
#define RKX120_CLK_TXESC_CSITX1_SEL_CLK_CPLL_MUX  1U
#define RKX120_CLK_TXESC_CSITX1_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON05(Offset:0x114)
#define RKX120_CLK_I2S_SRC_RKLINK_RX_DIV               0x08000005
#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL               0x020E0005
#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_CLK_TXPLL_MUX 0U
#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_CLK_CPLL_MUX  1U
#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON06(Offset:0x118)
#define RKX120_E0_CLK_RKLINK_RX_PRE_DIV               0x08000006
#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL               0x020E0006
#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_CLK_TXPLL_MUX 0U
#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_CLK_CPLL_MUX  1U
#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON07(Offset:0x11C)
#define RKX120_E1_CLK_RKLINK_RX_PRE_DIV               0x08000007
#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL               0x020E0007
#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_CLK_TXPLL_MUX 0U
#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_CLK_CPLL_MUX  1U
#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON08(Offset:0x120)
#define RKX120_CLK_PMA2PCS2LINK_CM_SEL                   0x01000008
#define RKX120_CLK_PMA2PCS2LINK_CM_SEL_CLK_LINK_PCS0_DFT 0U
#define RKX120_CLK_PMA2PCS2LINK_CM_SEL_CLK_LINK_PCS1_DFT 1U

// TXCRU_CLKSEL_CON10(Offset:0x128)
#define RKX120_CLK_PWM_TX_DIV               0x0800000A
#define RKX120_CLK_PWM_TX_SEL               0x020E000A
#define RKX120_CLK_PWM_TX_SEL_CLK_TXPLL_MUX 0U
#define RKX120_CLK_PWM_TX_SEL_CLK_CPLL_MUX  1U
#define RKX120_CLK_PWM_TX_SEL_XIN_OSC0_FUNC 2U

// TXCRU_CLKSEL_CON12(Offset:0x130)
#define RKX120_PCLKOUT_DVPTX_DIV               0x0800000C
#define RKX120_PCLKOUT_DVPTX_SEL               0x020E000C
#define RKX120_PCLKOUT_DVPTX_SEL_CLK_TXPLL_MUX 0U
#define RKX120_PCLKOUT_DVPTX_SEL_CLK_CPLL_MUX  1U
#define RKX120_PCLKOUT_DVPTX_SEL_XIN_OSC0_FUNC 2U

// ======================== TXCRU module definition END ========================
#define RKX120_CPS_INVAL                 0
#define RKX120_CPS_PLL_CPLL              1
#define RKX120_CPS_PLL_TXPLL             2
#define RKX120_CPS_DCLK_TX_GPIO0         3
#define RKX120_CPS_DCLK_TX_GPIO1         4
#define RKX120_CPS_CLK_TX_EFUSE          5
#define RKX120_CPS_CLK_PCS0_ADA          6
#define RKX120_CPS_CLK_PCS1_ADA          7
#define RKX120_CPS_CLK_CAPTURE_PWM_TX    8
#define RKX120_CPS_ICLK_C_CSI0           9
#define RKX120_CPS_ICLK_C_CSI1           10
#define RKX120_CPS_CLK_TXESC_CSITX0      COMPOSITE_CLK(RKX120_CLK_TXESC_CSITX0_SEL, RKX120_CLK_TXESC_CSITX0_DIV)
#define RKX120_CPS_CLK_TXESC_CSITX1      COMPOSITE_CLK(RKX120_CLK_TXESC_CSITX1_SEL, RKX120_CLK_TXESC_CSITX1_DIV)
#define RKX120_CPS_CLK_I2S_SRC_RKLINK_RX COMPOSITE_CLK(RKX120_CLK_I2S_SRC_RKLINK_RX_SEL, RKX120_CLK_I2S_SRC_RKLINK_RX_DIV)
#define RKX120_CPS_E0_CLK_RKLINK_RX_PRE  COMPOSITE_CLK(RKX120_E0_CLK_RKLINK_RX_PRE_SEL, RKX120_E0_CLK_RKLINK_RX_PRE_DIV)
#define RKX120_CPS_E1_CLK_RKLINK_RX_PRE  COMPOSITE_CLK(RKX120_E1_CLK_RKLINK_RX_PRE_SEL, RKX120_E1_CLK_RKLINK_RX_PRE_DIV)
#define RKX120_CPS_CLK_PMA2PCS2LINK_CM   COMPOSITE_CLK(RKX120_CLK_PMA2PCS2LINK_CM_SEL, 0)
#define RKX120_CPS_PCLKOUT_DVPTX         COMPOSITE_CLK(RKX120_PCLKOUT_DVPTX_SEL, RKX120_PCLKOUT_DVPTX_DIV)
#define RKX120_CPS_CLK_PWM_TX            COMPOSITE_CLK(RKX120_CLK_PWM_TX_SEL, RKX120_CLK_PWM_TX_DIV)
#define RKX120_CPS_BUSCLK_TX_PRE0        COMPOSITE_CLK(RKX120_BUSCLK_TX_PRE0_SEL, RKX120_BUSCLK_TX_PRE0_DIV)
#define RKX120_CPS_BUSCLK_TX_PRE         COMPOSITE_CLK(RKX120_BUSCLK_TX_PRE_SEL, 0)
#define RKX120_CPS_TEST_CLKOUT           COMPOSITE_CLK(RKX120_TEST_CLKOUT_IOUT_SEL, RKX120_TEST_CLKOUT_IOUT_DIV)
#endif
